| For more information, please contact Dr. William H. Robinson |
Last modified on April 26, 2005 |
|
EECE 277: FPGA Design
2005 Spring Semester
| Date | Lecture Topic | Assigned Reading | Special Event |
| Jan. 12 | What is FPGA Design? | Brown/Vranesic: Chapters 1 and 2 | |
| Jan. 14 | Design Methodologies | ||
| Jan. 17 | Gates and Boolean Algebra | Brown/Vranesic: Chapter 12 | Homework #1 Assigned |
| Jan. 19 | Computer-Aided Design (CAD) Tools | Brown/Vranesic: Chapter 3 | |
| Jan. 21 | NO CLASS | ||
| Jan. 24 | Implementation Technology | Brown/Vranesic: Appendices B, C, and D | Homework #1 Solutions |
| Jan. 26 | Implementation Technology Part 2 | Laboratory Assignment #1 | |
| Jan. 28 | Guest Lecture - Jason Scott | ||
| Jan. 31 | Interconnect and Logic Elements | ||
| Feb. 2 | In-Class Laboratory Day | Brown/Vranesic: Appendix A | Homework #2 Solutions |
| Feb. 4 | Guest Lecture - Philippe Adell | Homework #3 Assigned | |
| Feb. 7 | VHDL Philosophy 101 | Brown/Vranesic: Chapter 5 | Laboratory Assignment #1 Due |
| Feb. 9 | Introducing VHDL Constructs | ||
| Feb. 11 | More VHDL Constructs | ||
| Feb. 14 | Review for Exam 1 | Homework #3 Solutions | |
| Feb. 16 | EXAM 1 | ||
| Feb. 18 | Solutions to Exam 1 | Brown/Vranesic: Chapter 5 | Exam 1 Solutions |
| Feb. 21 | Number Representation and Adders | ||
| Feb. 23 | In-Class Laboratory Day | Brown/Vranesic: Chapter 6 | |
| Feb. 25 | Combinational Logic Blocks | Brown/Vranesic: Chapter 7 | Homework #4 Assigned |
| Feb. 28 | Storage Elements | Laboratory Assignment #2 Due | |
| Mar. 2 | Sequential Machines | Brown/Vranesic: Chapter 8 | |
| Mar. 4 | Examples of Digital System Design | Brown/Vranesic: Chapter 10 | |
| Mar. 7 | NO CLASS | SPRING BREAK | |
| Mar. 9 | NO CLASS | SPRING BREAK | |
| Mar. 11 | NO CLASS | SPRING BREAK | |
| Mar. 14 | Basic Computer Architecture | Laboratory Assignment #3 | |
| Mar. 16 | In-Class Laboratory Day | Homework #4 Solutions | |
| Mar. 18 | Verification and Testing | Brown/Vranesic: Chapter 11 | Last day to withdraw from course with a 'W' |
| Mar. 21 | Verification and Testing Part 2 | ||
| Mar. 23 | In-Class Laboratory Day | ||
| Mar. 25 | NO CLASS | ||
| Mar. 28 | Documentation for Project Design | Laboratory Assignment #3 Due | |
| Mar. 30 | Pseudo In-Class Laboratory Day | Proposal Guidelines | |
| Apr. 1 | Pipelining | ||
| Apr. 4 | Review for Exam 2 | Final Project Proposal Due | |
| Apr. 6 | EXAM 2 | ||
| Apr. 8 | Solutions to Exam 2 | Exam 2 Solutions | |
| Apr. 11 | Choosing the Right Device | ||
| Apr. 13 | In-Class Laboratory Day | ||
| Apr. 15 | VHDL Review | ||
| Apr. 18 | Reconfigurable Computing | ||
| Apr. 20 | In-Class Laboratory Day | ||
| Apr. 22 | Hardware/Software Co-Design | Report Guidelines | |
| Apr. 25 | Recap of FPGA Design | LAST DAY OF CLASS | |
| Apr. 27 | Final Project Demonstration Due | ||
| Apr. 30 | FINAL PROJECT PRESENTATIONS | Exam Time: 2pm - 5pm Final Project Report Due |
EECS Department | School of Engineering | Vanderbilt University
| For more information, please contact Dr. William H. Robinson |
Last modified on April 26, 2005 |
|
