8-Bit Binary Up/Down Counter

With Synchronous Load (LDN), Asynchronous Clear, and Asynchronous Load (SETN).

Generally, the presence of "N" (particularly at the end of the pin name) indicates Active-Low logic.

Functional Summary

GN         Counter enable pin

 

LDN       Synchronous load of A..H

 

CLRN    Async clear of A..H

 

SETN    Async load of A..H

 

DNUP    Up/Down counter setting. Low means count up.

 

Default Signal Levels

GND

• A..H
• GN
• CLK

VCC

• LDN
• DNUP
• SETN
• CLRN

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION 8count (clk, clrn, setn, ldn, dnup, gn, h, g, f, e, d, c, b, a) 

RETURNS (qh, qg, qf, qe, qd, qc, qb, qa, cout);

VHDL Component Declaration:

COMPONENT a_8count

   PORT (a, b, c, d, e, f, g, h, clk, clrn, setn: IN STD_LOGIC;

      ldn, dnup, gn: IN STD_LOGIC;

      cout, qa, qb, qc, qd, qe, qf, qg, qh: OUT STD_LOGIC);

END COMPONENT;